1. Technical Field
The present invention relates to a shift register circuit, a method of controlling a shift register, and a scanning line driving circuit, an active matrix apparatus, and an electronic device using the same.
2. Related Art
A JP-A-11-134893 (hereinafter, referred to as a patent document 1) discloses a shift register that has a clock control means corresponding to each stage of a shift unit circuit and is constructed such that a clock signal is supplied to the shift unit circuit only when a corresponding shift unit circuit is activated by this clock control means. According to this construction, it is possible to reduce power consumption. In the shift register disclosed in the patent document 1, one clock control means is provided for one stage of the shift register, and a clock control circuit has the same pitch as that of the shift register. This type of shift register is used as a driving circuit of a matrix type liquid crystal display device.
Recently, a display device is developed to have a higher precision. However, in order to provide a display area (a pixel area) having a higher precision according to necessity in a related art, the pitch of the shift register should be reduced accordingly. Therefore, a wiring arrangement of a corresponding clock control circuit should be changed according to the reduced pitch of the shift register. Generally, the clock control circuit is constructed of several tens of transistors, and has a complicated circuit arrangement. Although it is preferable for a display unit of a liquid crystal display panel mounted on a mobile phone and the like to have a narrow frame, the entire width of a driver circuit may be enlarged if a layout of the clock control circuit is designed based on a narrower pitch of a shift register. As a result, the frame of a display device may be enlarged accordingly.
In order to solve such a problem, a JP-A-2004-127509 (hereinafter, referred to as a patent document 2) discloses a shift register circuit, in which shift registers are divided into N circuit blocks along a length of stages, a clock control circuit is provided for each divided circuit block, and a predetermined number of the clock control circuits are controlled based on output signals from the latch circuits provided in the preceding and following stages of the corresponding circuit block. The shift register disclosed in the patent document 2 is advantageous in that the circuit size can be minimized and power consumption can be reduced, but also has shortcomings as follows.
Firstly, it is assumed that a series of pulses are transmitted to a certain circuit block. In this case, when the pulse signal is transmitted to the last stage of the (N−1)th circuit block, the clock control circuit of the Nth stage is activated by detecting the output signal from the last stage of the (N−1)th circuit block, and the clock signal is supplied to the Nth circuit block. When a head pulse is transmitted to the latch circuit provided in the second stage of the Nth circuit block, and its output signal is activated, a reset signal is supplied to the clock control circuit of the (N−1)th stage, and the clock signal supplied to the (N−1)th circuit block stops. In other words, the second and subsequent pulses are not transmitted to the Nth stage, and the pulse signal stays in the (N−1)th circuit block. Although such a problem may not occur if one pulse is transmitted per one time, the shift register disclosed in the patent document 2 cannot satisfy various kinds of requirements for the driving method that are being recently used. For example, if it is required that a plurality of pulses should be simultaneously transmitted to one circuit block, the shift register disclosed in the patent document 2 cannot satisfy this requirement.